Phase locked loop (PLL) is often used to implement frequency synthesizers in various wireless communication systems. A frequency synthesizer is an electronic system that translates an input signal at a reference frequency to an output signal at a different frequency. The various specifications of a frequency synthesizer such as output frequency range, stability, bandwidth, noise, speed and power characterize a design of the frequency synthesizer.
The performance of an integer-N frequency synthesizer can be reasonably predicted with good accuracy and it is simple to design. However, the integer-N frequency synthesizer has some limitations. For stable operation, the PLL loop bandwidth is constrained by the reference frequency, which is defined by frequency resolution of a wireless communication system. Such narrow bandwidth requirement translates into slower loop settling behavior and less suppression of VCO phase noise. This limits the usefulness of the integer-N frequency synthesizer. Hence, the focus of industry changed to fractional-N synthesizers which allow a wide loop bandwidth and achieve fine frequency resolution simultaneously. In addition, a fractional-N synthesizer can support range of reference frequencies.
However, fractional-N synthesizers suffer from multiple drawbacks such as: (a) performance degradation due to quantization noise of a sigma delta modulator used in the fractional-N synthesizers; (b) noise of charge pump is a major phase noise contributor in low power implementations; and/or (c) variation in bandwidth causes noise to degrade.
The existing solutions to address these drawbacks include use of a highly linear charge pump. But this leads to increased current and noise due to additional hardware. Another solution is to use linearization techniques such as offset PFD (phase/frequency detector), dual PFD and gated offset PFD. These techniques have several disadvantages such as increased reference spur, and additional complexity to generate accurate timing.